DDR5 RDIMM Verification IP

Truechip's DDR5 RDIMM Verification IP provides an effective & efficient way to verify the components interfacing with DDR5 RDIMM interface of an ASIC/FPGA or SoC. Truechip's DDR5 RDIMM VIP is fully compliant with Standard DDR5 specification from JEDEC. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
• Unique development methodology to ensure highest levels of quality.
• 24X5 customer support & response under 90 Min.
• Unique and customizable licensing models.
• Exhaustive set of assertions and cover points with connectivity example for all the components.
• Consistency of interface, installation, operation and documentation across all our VIPs.
• Provide complete solution and easy

Features

• Compliant to JEDEC DDR5 SDRAM & DDR5 RCD Specification.
• Supports connection to any DDR5 Memory Controller IP communicating with a JEDEC compliant DDR5 Memory Model.
• Supports configurable SDRAM addressing of different sizes (x4, x8 and x16).
• Available in all memory sizes from up to 64 Gb.
• Supports all Command Address Rates (SDR1, SDR2 & DDR).
• Supports Output Inversion and Mirroring.
• Supports training modes: DCSTM, QCSTM, DCATM, EDCATM, QCATM.
• Supports Transparent Mode, VHost Mode, CA Validation Pass-Through Mode. AXI Seq AXI Master APB/AHB seq APB/AHB Master APB/AHB In DFI In Memory Controller BFM/DUT DFI Monitor Functional Coverage Asser ons Transac on Logger DDR In DFI-PHY BFM/DUT APB Master APB Seq DFI Monitor Functional Coverage Asser ons Transac on Logger Memory BFM/DUT I2C SPD TS PMIC DIMMs
• Supports Control words decode, read, directed and paged access.
• Supports 3DS with command to command timings checks in SLR & DLR.
• Supports Data Masking (DM).
• Supports Cyclic Redundancy Check (CRC).
• Support for all speed-grades/speed-bins.
• Supports Programmable burst lengths (BC8, BL16, BL32, BL32 OTF).
• Supports configurable timing parameters and rank associations.
• Supports capturing all the valid DDR5 commands including Activate, Read Write, Precharge.
• Supports CA parity for command/address bus.
• Supports Power-up Reset and initialization sequences.
• Supports Precharge Power-Down, Active Power-Down, Self-Refresh (with and without Clock Stop) operation.
• Reports various timing errors, which can be used to check any timing violations.
• Provides full control to the user to enable/disable various types of messages.
• Supports full timing models or bus functional models.
• Support for Multiple Ranks architecture.
• Supports advanced System Verilog features like constrained random testing.
• Supports dynamically configurable modes.
• Strong Protocol Monitor with real time exhaustive programmable checks.
• Supports Dynamic as well as Static Error Injection scenarios.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
• Graphical analyzer to show transactions for easy debugging.

Deliverables

• DDR5-SDRAM Model, RCD Model & Data Buffer Model
• DDR5 Monitor & Scoreboard
• DDR5 Memory Controller BFM/Agent
• DDR5 PHY BFM model
• DDR5 Phy Monitor and Scoreboard
• Test-Bench Configurations
• Test Suite (Available in Source code)
  • Basic Protocol Tests
  • Directed & Random Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes